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features ? 524,288 x 8 only single power supply operation - 5.0v only operation for read, erase and program op- eration fast access time: 55/70/90ns ? compatible with mx29f040 device low power consumption - 30ma maximum active current(5mhz) - 1ua typical standby current command register architecture - byte programming (9us typical) - sector erase 8 equal sectors of 64k-byte each auto erase (chip & sector) and auto program - automatically erase any combination of sectors with erase suspend capability - automatically program and verify data at specified address erase suspend/erase resume - suspends an erase operation to read data from, or program data to, another sector that is not being erased, erase and programming, while maintaining maximum eprom compatibility. mxic flash technology reliably stores memory con- tents even after 100,000 erase and program cycles. the mxic cell is designed to optimize the erase and program mechanisms. in addition, the combi- nation of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. the mx29f040c uses a 5.0v 10% vcc supply to per- form the high reliability erase and auto program/ erase algorithms. the highest degree of latch-up protection is achieved with mxic's proprietary non-epi process. latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1v to vcc + 1v. general description the mx29f040c is a 4-mega bit flash memory orga- nized as 512k bytes of 8 bits. mxic's flash memories offer the most cost-effective and reliable read/write non- volatile random access memory. the mx29f040c is packaged in 32-pin plcc, tsop, pdip. it is designed to be reprogrammed and erased in system or in standard eprom programmers. the standard mx29f040c offers access time as fast as 55ns, allowing operation of high-speed microprocessors without wait states. to eliminate bus contention, the mx29f040c has separate chip enable (ce#) and output enable (oe#) controls. mxic's flash memories augment eprom functionality with in-circuit electrical erasure and programming. the mx29f040c uses a command register to manage this functionality. the command register allows for 100% ttl level control inputs and fixed power supply levels during then resumes the erase status reply - data# polling & toggle bit for detection of program and erase cycle completion sector protect/chip unprotect for 5v only system sector protection - hardware method to disable any combination of sec- tors from program or erase operations - temporary sector unprotect allows code changes in previously locked sectors 100,000 minimum erase/program cycles 100,000 minimum erase/program cycles latch-up protected to 100ma from -1v to vcc+1v low vcc write inhibit is equal to or less than 3.2v package type: - 32-pin plcc, tsop or pdip - all pb-free devices are rohs compliant compatibility with jedec standard - pinout and software compatible with single-power supply flash 20 years data retention 1 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c 4m-bit [512k x 8] cmos single voltage 5v only equal sector flash memory
2 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c pin configurations 32 plcc 32 tsop (standard type) (8mm x 20mm) symbol pin name a0~a18 address input q0~q7 data input/output ce# chip enable input we# write enable input oe# output enable input gnd ground pin vcc +5.0v single power supply pin description sector a18 a17 a16 address range sa0 0 0 0 00000h-0ffffh sa1 0 0 1 10000h-1ffffh sa2 0 1 0 20000h-2ffffh sa3 0 1 1 30000h-3ffffh sa4 1 0 0 40000h-4ffffh sa5 1 0 1 50000h-5ffffh sa6 1 1 0 60000h-6ffffh sa7 1 1 1 70000h-7ffffh note: all sectors are 64 kbytes in size. sector structure mx29f040c sector address table 32 pdip mx29f040c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a18 a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 gnd 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 vcc we# a17 a14 a13 a8 a9 a11 oe# a10 ce# q7 q6 q5 q4 q3 1 4 5 9 13 14 17 20 21 25 29 32 30 a14 a13 a8 a9 a11 oe# a10 ce# q7 a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 gnd q3 q4 q5 q6 a12 a15 a16 a18 vcc we# a17 mx29f040c a11 a9 a8 a13 a14 a17 we# vcc a18 a16 a15 a12 a7 a6 a5 a4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 oe# a10 ce# q7 q6 q5 q4 q3 gnd q2 q1 q0 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 mx29f040c
3 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c block diagram control input logic program/erase high voltage write s tat e machine (wsm) s tat e register flash array x-decoder address latch and buffer y-pass gate y-decoder array source hv command data decoder command data latch i/o buffer pgm data hv program data latch sense amplifier q0-q7 a0-a18 ce# oe# we#
4 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c automatic programming the mx29f040c is byte programmable using the auto- matic programming algorithm. the automatic program- ming algorithm makes the external system do not need to have time out sequence nor to verify the data pro- grammed. the typical chip programming time at room temperature of the mx29f040c is less than 4.5 sec- onds. automatic chip erase the entire chip is bulk erased using 10 ms erase pulses according to mxic's automatic chip erase algorithm. typical erasure at room temperature is accomplished in less than 4 second. the automatic erase algorithm au- tomatically programs the entire array prior to electrical erase. the timing and verification of electrical erase are controlled internally within the device. automatic sector erase the mx29f040c is sector(s) erasable using mxic's auto sector erase algorithm. sector erase modes allow sectors of the array to be erased in one erase cycle. the automatic sector erase algorithm auto- matically programs the specified sector(s) prior to electrical erase. the timing and verification of electri- cal erase are controlled internally within the device. automatic programming algorithm mxic's automatic programming algorithm require the user to only write program set-up commands (including 2 un- lock write cycle and a0h) and a program command (pro- gram data and address). the device automatically times the programming pulse width, provides the program veri- fication, and counts the number of sequences. a status bit similar to data# polling and a status bit toggling be- tween consecutive read cycles, provide feedback to the user as to the status of the programming operation. automatic erase algorithm mxic's automatic erase algorithm requires the user to write commands to the command register using stand- ard microprocessor write timings. the device will auto- matically pre-program and verify the entire array. then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. a status bit toggling between consecutive read cycles provides feedback to the user as to the sta- tus of the programming operation. register contents serve as inputs to an internal state- machine which controls the erase and programming cir- cuitry. during write cycles, the command register inter- nally latches address and data needed for the program- ming and erase operations. during a system write cycle, addresses are latched on the falling edge of we# or ce#, whichever happens later, and data are latched on the rising edge of we# or ce#, whichever happens first. mxic's flash technology combines years of eprom experience to produce the highest levels of quality, relia- bility, and cost effectiveness. the mx29f040c electri- cally erases all bits simultaneously using fowler-nord- heim tunneling. the bytes are programmed by using the eprom programming mechanism of hot electron injec- tion. during a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. during a sector erase cycle, the command register will only respond to erase suspend command. after erase suspend is completed, the device stays in read mode. after the state machine has completed its task, it will allow the command regis- ter to respond to its full command set.
5 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c first bus second bus third bus fourth bus fifth bus sixth bus command bus cycle cycle cycle cycle cycle cycle cycle addr data addr data addr data addr data addr data addr data reset 1 xxxh f0h read 1 ra rd read silicon id 4 555h aah 2aah 55h 555h 90h adi ddi sector protect verify 4 555h aah 2aah 55h 555h 90h (sa)x 00h 02 01h program 4 555h aah 2aah 55h 555h a0h pa pd chip erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h sector erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h sector erase suspend 1 xxxh b0h sector erase resume 1 xxxh 30h unlock for sector 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 20h protect/unprotect table 1. software command definitions note: 1. adi = address of device identifier; a1=0, a0 = 0 for manufacture code,a1=0, a0 = 1 for device code a2-a18=do not care. (refer to table 3) ddi = data of device identifier : c2h for manufacture code, a4h for device code. x = x can be vil or vih ra=address of memory location to be read. rd=data to be read at location ra. 2. pa = address of memory location to be programmed. pd = data to be programmed at location pa. sa = address to the sector to be erased. 3. the system should generate the following address patterns: 555h or 2aah to address a10~a0 . address bit a11~a18=x=don't care for all address commands except for program address (pa) and sector address (sa). write sequence may be initiated with a11~a18 in either state. 4. for sector protect verify operation : if read out data is 01h, it means the sector has been protected. if read out data is 00h, it means the sector is still not being protected. command definitions device operations are selected by writing specific address and data sequences into the command register. writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. table 1 defines the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. either of the two reset command sequences will reset the device (when applicable).
6 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c pins mode ce# oe# we# a0 a1 a6 a9 q0 ~ q7 read silicon id l l h l l x v id (2) c2h manufacturer code(1) read silicon id l l h h l x v id (2) a4h device code(1) read l l h a0 a1 a6 a9 d out standby h x x x x x x high z output disable l h h x x x x high z write l h l a0 a1 a6 a9 d in (3) sector protect without 12v l h l x x l h x system (6) chip unprotect without 12v l h l x x h h x system (6) verify sector protect/unprotect l l h x h x h code(5) without 12v system (7) reset x x x x x x x high z table 2. mx29f040c bus operation notes : 1. manufacturer and device codes may also be accessed via a command register write sequence. refer to table 1. 2. vid is the silicon-id-read high voltage, 11.5v to 12.5v. 3. refer to table 1 for valid data-in during a write operation. 4. x can be vil or vih. 5. code=00h means unprotected. code=01h means protected. a18~a16=sector address for sector protect. 6. refer to sector protect/unprotect algorithm and waveform. must issue "unlock for sector protect/unprotect" command before "sector protect/unprotect without 12v system" command. 7. the "verify sector protect/unprotect without 12v system" is only following "sector protect/unprotect without 12v system" command.
7 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c read/reset command the read or reset operation is initiated by writing the read/ reset command sequence into the command register. microprocessor read cycles retrieve array data. the de- vice remains enabled for reads until the command regis- ter contents are altered. if program-fail or erase-fail happen, the write of f0h will reset the device to abort the operation. a valid com- mand must then be written to place the device in the desired state. silicon-id-read command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manu- facturer and device codes must be accessible while the device resides in the target system. prom program- mers typically access signature codes by raising a9 to a high voltage. however, multiplexing high voltage onto address lines is not generally desired system design prac- tice. the mx29f040c contains a silicon-id-read operation to supplement traditional prom programming methodol- ogy. the operation is initiated by writing the read silicon id command sequence into the command register. fol- lowing the command write, a read cycle with a1=vil,a0=vil retrieves the manufacturer code of c2h. a read cycle with a1=vil, a0=vih returns the device code of a4h for mx29f040c. set-up automatic chip/sector erase chip erase is a six-bus cycle operation. there are two "unlock" write cycles. these are followed by writing the "set-up" command 80h. two more "unlock" write cycles are then followed by the chip erase command 10h. the automatic chip erase does not require the device to be entirely pre-programmed prior to executing the auto- matic chip erase. upon executing the automatic chip erase, the device will automatically program and verify the entire memory for an all-zero data pattern. when the device is automatically verified to contain an all-zero pattern, a self-timed chip erase and verify begin. the erase and verify operations are completed when the data on q7 is "1" at which time the device returns to the read mode. the system is not required to provide any control or timing during these operations. when using the automatic chip erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). if the erase operation was unsuccessful, the data on q5 is "1"(see table 4), indicating the erase operation ex- ceed internal timing limit. the automatic erase begins on the rising edge of the last we# or ce#, whichever happens first pulse in the com- mand sequence and terminates when the data on q7 is "1" and the data on q6 stops toggling for two consecu- tive read cycles, at which time the device returns to the read mode. pins a0 a1 q7 q6 q5 q4 q3 q2 q1 q0 code (hex) manufacture code vil vil 1 1 0 0 0 0 1 0 c2h device code for mx29f040c vih vil 1 0 1 0 0 1 0 0 a4h sector protection verification x vih 0 0 0 0 0 0 0 1 01h (protected) x vih 0 0 0 0 0 0 0 0 00h(unprotected) table 3. expanded silicon id code
8 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c sector erase commands the automatic sector erase does not require the device to be entirely pre-programmed prior to executing the au- tomatic set-up sector erase command and automatic sector erase command. upon executing the automatic sector erase command, the device will automatically pro- gram and verify the sector(s) memory for an all-zero data pattern. the system is not required to provide any con- trol or timing during these operations. when the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verify begin. the erase and verify operations are complete when the data on q7 is "1" and the data on q6 stops toggling for two consecutive read cycles, at which time the device returns to the read mode. the system is not required to provide any control or timing during these op- erations. when using the automatic sector erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). sector erase is a six-bus cycle operation. there are two "unlock" write cycles. these are followed by writing the set-up com- mand 80h. two more "unlock" write cycles are then fol- lowed by the sector erase command 30h. the sector address is latched on the falling edge of we# or ce#, whichever happens later, while the command (data) is latched on the rising edge of we# or ce#, whichever happens first. sector addresses selected are loaded into internal register on the sixth falling edge of we# or ce#, whichever happens later. each successive sector load cycle started by the falling edge of we# or ce#, whichever happens later must begin within 30us from the rising edge of the preceding we# or ce#, whichever happens first. otherwise, the loading period ends and internal auto sector erase cycle starts. (monitor q3 to determine if the sector erase timer window is still open, see section q3, sector erase timer.) any command other than sector erase (30h) or erase suspend (b0h) during the time-out period resets the device to read mode. status q7 q6 q5 q3 q2 note1 note2 byte program in auto program algorithm q7# toggle 0 n/a no t oggle auto erase algorithm 0 toggle 0 1 toggle erase suspend read 1 no 0 n/a toggle in progress (erase suspended sector) toggle erase suspended mode erase suspend read data data data data data (non-erase suspended sector) erase suspend program q7# toggle 0 n/a n/a byte program in auto program algorithm q7# toggle 1 n/a no t oggle exceeded auto erase algorithm 0 toggle 1 1 toggle time limits erase suspend program q7# toggle 1 n/a n/a table 4. write operation status note: 1. q7 and q2 require a valid address when reading status information. refer to the appropriate subsection for further details. 2. q5 switches to '1' when an auto program or auto erase operation has exceeded the maximum timing limits. see "q5:exceeded timing limits " for more information.
9 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c erase suspend this command only has meaning while the state ma- chine is executing automatic sector erase operation, and therefore will only be responded during automatic sector erase operation. when the erase suspend command is written during a sector erase operation, the device re- quires a maximum of 20us to suspend the erase opera- tions. however, when the erase suspend command is written during the sector erase time-out, the device im- mediately terminates the time-out period and suspends the erase operation. after this command has been ex- ecuted, the command register will initiate erase suspend mode. the state machine will return to read mode auto- matically after suspend is ready. at this time, state ma- chine only allows the command register to respond to the read memory array, erase resume and program commands. the system can determine the status of the program operation using the q7 or q6 status bits, just as in the standard program operation. after an erase-suspend pro- gram operation is complete, the system can once again read array data within non-suspended sectors. erase resume this command will cause the command register to clear the suspend state and return back to sector erase mode but only if an erase suspend command was previously issued. erase resume will not have any effect in all other conditions. another erase suspend command can be written after the chip has resumed erasing. however, a 400us time delay must be required after the erase re- sume command, if the system implements an endless erase suspend/resume loop, or the number of erase sus- pend/resume is exceeded 1024 times. the erase times will be expended if the erase behavior always be sus- pended. set-up automatic program commands to initiate automatic program mode, a three-cycle com- mand sequence is required. there are two "unlock" write cycles. these are followed by writing the automatic pro- gram command a0h. once the automatic program command is initiated, the next we# or ce# pulse causes a transition to an active programming operation. addresses are latched on the falling edge, and data are internally latched on the rising edge of the we# or ce#, whichever happens first pulse. the rising edge of we# or ce#, whichever hap- pens first also begins the programming operation. the system is not required to provide further controls or tim- ings. the device will automatically provide an adequate internally generated program pulse and verify margin. if the program operation was unsuccessful, the data on q5 is "1"(see table 4), indicating the program operation exceed internal timing limit. the automatic programming operation is completed when the data read on q6 stops toggling for two consecutive read cycles and the data on q7 and q6 are equivalent to data written to these two bits, at which time the device returns to the read mode (no program verify command is required). data# polling-q7 the mx29f040c also features data# polling as a method to indicate to the host system that the automatic pro- gram or erase algorithms are either in progress or com- pleted. while the automatic programming algorithm is in opera- tion, an attempt to read the device will produce the comple- ment data of the data last written to q7. upon comple- tion of the automatic program algorithm an attempt to read the device will produce the true data last written to q7. the data# polling feature is valid after the rising edge of the fourth we# or ce#, whichever happens first pulse of the four write pulse sequences for automatic pro- gram. while the automatic erase algorithm is in operation, q7 will read "0" until the erase operation is competed. upon completion of the erase operation, the data on q7 will read "1". the data# polling feature is valid after the ris- ing edge of the sixth we# or ce#, whichever happens first pulse of six write pulse sequences for automatic chip/sector erase. the data# polling feature is active during automatic pro- gram/erase algorithm or sector erase time-out. (see sec- tion q3 sector erase timer)
10 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c the rising edge of the final we# or ce#, whichever hap- pens first pulse in the command sequence. q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe# or ce# to control the read cycles.) but q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. q6, by com- parison, indicates whether the device is actively eras- ing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sectors and mode information. refer to table 4 to compare outputs for q2 and q6. reading toggle bits q6/ q2 whenever the system initially begins reading toggle bit status, it must read q7-q0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has com- pleted the program or erase operation. the system can read array data on q7-q0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of q5 is high (see the section on q5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as q5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase opera- tion. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that system initially determines that the toggle bit is toggling and q5 has not gone high. the system may continue to monitor the toggle bit and q5 through successive read cycles, determining the sta- tus as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the al- gorithm when it returns to determine the status of the operation. q6:toggle bit i toggle bit i on q6 indicates whether an automatic pro- gram or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# or ce#, whichever happens first pulse in the command sequence (prior to the program or erase operation), and during the sector time-out. during an automatic program or erase algorithm opera- tion, successive read cycles to any address cause q6 to toggle. the system may use either oe# or ce# to control the read cycles. when the operation is complete, q6 stops toggling. after an erase command sequence is written, if all sec- tors selected for erasing are protected, q6 toggles and returns to reading array data. if not all selected sectors are protected, the automatic erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use q6 and q2 together to determine whether a sector is actively erasing or is erase suspended. when the device is actively erasing (that is, the auto- matic erase algorithm is in progress), q6 toggling. when the device enters the erase suspend mode, q6 stops toggling. however, the system must also use q2 to de- termine which sectors are erasing or erase-suspended. alternatively, the system can use q7. if a program address falls within a protected sector, q6 toggles for approximately 2us after the program command sequence is written, then returns to reading array data. q6 also toggles during the erase-suspend-program mode, and stops toggling once the automatic program algorithm is complete. table 4 shows the outputs for toggle bit i on q6. q2:toggle bit ii the "toggle bit ii" on q2, when used with q6, indicates whether a particular sector is actively erasing (that is, the automatic erase algorithm is in process), or whether that sector is erase-suspended. toggle bit i is valid after
11 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c q5 exceeded timing limits q5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). under these conditions q5 will produce a "1". this time-out condition indicates that the program or erase cycle was not suc- cessfully completed. data# polling and toggle bit are the only operating functions of the device under this con- dition. if this time-out condition occurs during sector erase op- eration, it specifies that a particular sector is bad and it may not be reused. however, other sectors are still func- tional and may be used for the program or erase opera- tion. the device must be reset to use other sectors. write the reset command sequence to the device, and then execute program or erase command sequence. this allows the system to continue to use the other active sectors in the device. if this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or com- bination of sectors are bad. if this time-out condition occurs during the byte program- ming operation, it specifies that the entire sector con- taining that byte is bad and this sector may not be re- used, (other sectors are still functional and can be re- used). the time-out condition may also appear if a user tries to program a non blank location without erasing. in this case the device locks out and never completes the au- tomatic algorithm operation. hence, the system never reads a valid data on q7 bit and q6 never stops toggling. once the device has exceeded timing limits, the q5 bit will indicate a "1". please note that this is not a device failure condition since the device was incorrectly used. data protection the mx29f040c is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transi- tion. during power up the device automatically resets the state machine in the read mode. in addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of spe- cific command sequences. the device also incorporates several features to prevent inadvertent write cycles re- sulting from vcc power-up and power-down transition or system noise. q3 sector erase timer after the completion of the initial sector erase command sequence, the sector erase time-out will begin. q3 will remain low until the time-out is complete. data# polling and toggle bit are valid after the initial sector erase com- mand sequence. if data# polling or the toggle bit indicates the device has been written with a valid erase command, q3 may be used to determine if the sector erase timer window is still open. if q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by data# polling or toggle bit. if q3 is low ("0"), the device will accept addi- tional sector erase commands. to insure the command has been accepted, the system software should check the status of q3 prior to and following each subsequent sector erase command. if q3 were high on the second status check, the command may not have been accepted. write pulse "glitch" protection noise pulses of less than 5ns (typical) on ce# or we# will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe# = vil, ce# = vih or we# = vih. to initiate a write cycle ce# and we# must be a logical zero while oe# is a logical one. power supply decoupling in order to reduce power switching effect, each device should have a 0.1uf ceramic capacitor connected be- tween its vcc and gnd.
12 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c power-up sequence the mx29f040c powers up in the read only mode. in addition, the memory contents may only be altered after successful completion of the predefined command se- quences. sector protection without 12v sys- tem the mx29f040c also feature a sector protection method in a system without 12v power supply. the programming equipment do not need to supply 12 volts to protect sec- tors. the details are shown in sector protect algorithm and waveform. chip unprotect without 12v system the mx29f040c also feature a chip unprotection method in a system without 12v power supply. the programming equipment do not need to supply 12 volts to unprotect all sectors. the details are shown in chip unprotect algo- rithm and waveform.
13 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c notes : 1. vil min. = -1.0v for pulse width is equal to or less than 50 ns. vil min. = -2.0v for pulse width is equal to or less than 20 ns. 2. vih max. = vcc + 1.5v for pulse width is equal to or less than 20 ns. if vih is over the specified maximum value, read operation cannot be guaranteed. read operation dc characteristics (ta = -40 o c to 85 o c, vcc = 5v 10%) symbol parameter min. typ max. unit conditions ili input leakage current 1 ua vin = gnd to vcc ilo output leakage current 10 ua vout = gnd to vcc isb1 standby vcc current 1 ma ce# = vih isb2 1 5 ua ce# = vcc + 0.3v icc1 operating vcc current 30 ma iout = 0ma, f=5mhz icc2 50 ma iout = 0ma, f=10mhz vil input low voltage -0.3 (note 1) 0.8 v vih input high voltage 0.7xvcc vcc + 0.3 v vol output low voltage 0.45 v iol = 2.1ma, vcc=vcc min voh1 output high voltage(ttl) 2.4 v ioh = -2ma, vcc=vcc min voh2 output high voltage(cmos) vcc-0.4 v ioh = -100ua,vcc=vcc min capacitance (ta = 25 o c, f = 1.0 mhz) symbol parameter min. typ max. unit conditions cin1 input capacitance 8 pf vin = 0v cin2 control pin capacitance 12 pf vin = 0v cout output capacitance 12 pf vout = 0v
14 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c note : 1. tdf is defined as the time at which the output achieves the open circuit condition and data is no longer driven. 29f040c-55 29F040C-70 29f040c-90 symbol parameter min. max. min. max. min. max. unit conditions tacc address to output delay 55 70 90 ns ce#=oe#=vil tce ce# to output delay 55 70 90 ns oe#=vil toe oe# to output delay 30 30 35 ns ce#=vil tdf oe# high to output float 0 20 0 20 0 20 ns ce#=vil (note 1) toh address to output hold 0 0 0 ns ce#=oe#=vil ac characteristics (ta =-40 o c to 85 o c, vcc = 5v 10%) test conditions: input pulse levels: 0.45v/0.7xvcc for 70ns & 90ns, 0v/0.7xvcc for 55ns input rise and fall times: is equal to or less than 10ns for 70ns & 90ns, 5ns for 55ns output load: 1 ttl gate + 100pf (including scope and jig) for 70ns & 90ns, 1ttlgate+30pf for 55ns max. reference levels for measuring timing: 0.8v, 2.0v for 70ns & 90ns,1.5v for 55ns
15 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c absolute maximum ratings rating value ambient operating temperature -40 o c to 85 o c storage temperature -65 o c to 125 o c ambient temperature with power -55 o c to 125 o c applied applied input voltage -0.5v to 7.0v applied output voltage -0.5v to 7.0v vcc to ground potential -0.5v to 7.0v a9 -0.5v to 13.5v notice: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional op- erational sections of this specification is not implied. ex- posure to absolute maximum rating conditions for ex- tended period may affect reliability. notice: specifications contained within the following tables are subject to change. read timing waveforms notes: 1. vil min. = -0.6v for pulse width is equal to or less than 20ns. 2. if vih is over the specified maximum value, programming operation cannot be guaranteed. 3. icces is specified with the device de-selected. if the device is read during erase suspend mode, current draw is the sum of icces and icc1 or icc2. 4. all current are in rms unless otherwise noted. dc characteristics (ta = -40 o c to 85 o c, vcc = 5v 10%) symbol parameter min. typ max. unit conditions icc1 (read) operating vcc current 30 ma iout=0ma, f=5mhz icc2 50 ma iout=0ma, f=10mhz icc3 (program) 50 ma in programming icc4 (erase) 50 ma in erase icces vcc erase suspend current 2 ma ce#=vih, erase suspended command programming/data programming/erase operation addresses ce# oe# tacc we# vih vil vih vil vih vil vih vil voh vol high z high z data valid toe tdf tce outputs toh add valid
16 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c ac characteristics ta = -40 o c to 85 o c, vcc = 5v 10% speed option symbol parameter 55(note 2) 70 90 unit toes oe# setup time min. 0 0 0 ns tcwc command programming cycle min. 55 70 90 ns tcep we# programming pulse width min. 35 35 45 ns tceph we# programming pulse width high min. 20 20 20 ns tas address setup time min. 0 0 0 ns tah address hold time min. 45 45 45 ns tds data setup time min. 30 30 45 ns tdh data hold time min. 0 0 0 ns tcesc ce# setup time before command write min. 0 0 0 ns tdf output disable time (note 1) max. 20 20 20 ns taetc erase time in auto chip erase typ. 4 4 4 s max. 32 32 32 s taetb erase time in auto sector erase typ. 0.7 0.7 0.7 s max. 15 15 15 s tavt programming time in auto verify typ. 9 9 9 us max. 300 300 300 us tbal sector address load time min. 50 50 50 us tch ce# hold time min. 0 0 0 ns tcs ce# setup to we# going low min. 0 0 0 ns notes: 1. tdf defined as the time at which the output achieves the open circuit condition and data is no longer driven. 2. under condition of vcc=5v 10%,cl=30pf,vih/vil=0.7xvcc/0v,voh/vol=1.5v/1.5v,iol=2ma,ioh=2ma.
17 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c switching test circuits switching test waveforms for 29F040C-70 and 29f040c-90 switching test waveforms for 29f040c-55 device under test diodes=in3064 or equivalent cl 6.2k ohm 2.7k ohm +5v cl=100pf including jig capacitance for 70ns and 90ns cl=30pf including jig capacitance for 55ns 2.0v 2.0v 0.8v 0.8v test points 0.7xvcc 0.45v ac testing: inputs are driven at 0.7xvcc for a logic "1" and 0.45v for a logic "0". input pulse rise and fall times are < 10ns. output input 1.5v 1.5v test points 0.7xvcc 0v ac testing: inputs are driven at 0.7xvcc for a logic "1" and 0v for a logic "0". input pulse rise and fall times are < 5ns. output input
18 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c command write timing waveform addresses ce# oe# we# din tds tah data tdh tcs tch tcwc tceph1 tcep toes tas vcc 5v vih vil vih vil vih vil vih vil vih vil add valid
19 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c one byte data is programmed. verify in fast algorithm and additional programming by external control are not required because these operations are executed auto- matically by internal control circuit. programming comple- tion can be verified by data# polling and toggle bit check- automatic programming timing waveform ing after automatic verification starts. device outputs data# during programming and data# after programming on q7.(q6 is for toggle bit; see toggle bit, data# polling, timing waveform) automatic programming timing waveform tcwc tas tcep tds tdh tdf vcc 5v ce# oe# q0,q1,q2 q4(note 1) we# a11~a18 tceph tah add valid tcesc q7 command in add valid a0~a10 command in command in data in data command in command in command in data in data data # tavt toe data# polling 2aah 555h 555h (q0~q7) command #55h command #a0h note : (1). q6:toggle bit, q5:timing-limit bit, q3: time-out bit command #aah
20 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c automatic programming algorithm flowchart start write data aah address 555h write data 55h address 2aah write program data/address write data a0h address 555h yes no toggle bit checking q6 not toggled verify byte ok yes q5 = 1 reset auto program completed auto program exceed timing limit no invalid command yes no .
21 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c all data in chip are erased. external erase verification is not required because data is erased automatically by internal control circuit. erasure completion can be veri- fied by data# polling and toggle bit checking after automatic erase starts. device outputs 0 during erasure and 1 after erasure on q7.(q6 is for toggle bit; see toggle bit, data# polling, timing waveform) automatic chip erase timing waveform automatic chip erase timing waveform tcwc tas tcep tds tdh vcc 5v ce# oe# q0,q1, q4(note 1) we# a11~a18 tceph tah q7 command in a0~a10 command in command in command in command in command in taetc data# polling 2aah 555h 555h command #aah command #55h command #80h (q0~q7) note : (1). q6:toggle bit, q5:timing-limit bit, q3: time-out bit, q2: toggle bit 555h 2aah 555h command in command in command #aah command in command in command #55h command in command in command #10h
22 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c automatic chip erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h yes no toggle bit checking q6 not toggled write data 10h address 555h write data 55h address 2aah reset auto chip erase exceed timing limit data# polling q7 = 1 yes q5 = 1 auto chip erase completed . no invalid command yes
23 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c sector data indicated by a16 to a18 are erased. external erase verify is not required because data are erased automatically by internal control circuit. erasure comple- tion can be verified by data# polling and toggle bit checking after automatic erase starts. device outputs 0 during erasure and 1 after erasure on q7.(q6 is for toggle bit; see toggle bit, data# polling, timing waveform) automatic sector erase timing waveform automatic sector erase timing waveform tah sector address0 555h 2aah 2aah 555h 555h sector address1 sector addressn vcc 5v ce# oe# q0,q1, q4(note 1) we# a16-a18 q7 a0~a10 command in command in command in command in command in command in command in command in command in command in command in command in command in command in command #30h command #30h command #30h command #55h command #aah command #80h command #55h command #aah (q0~q7) command in command in tdh tds tcep tcwc taetb tbal data# polling tceph tas note : (1). q6:toggle bit, q5:timing-limit bit, q3: time-out bit, q2: toggle bit
24 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c automatic sector erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h yes no toggle bit checking q6 not toggled write data 30h sector address write data 55h address 2aah reset auto sector erase exceed timing limit data# polling q7 = 1 q5 = 1 . auto sector erase completed load other sector addrss if necessary (load other sector address) yes no last sector to erase time-out bit checking q3=1 ? toggle bit checking q6 toggled ? invalid command no yes yes no
25 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c erase suspend/erase resume flowchart note: if the system implements an endless erase suspend/resume loop, or the number of erase suspend/resume is exceeded 1024 times, then the 400us time delay must be put into consideration. start write data b0h toggle bit checking q6 not toggled erase suspend yes no write data 30h delay 400us (note) continue erase reading or programming end read array or program another erase suspend ? no yes yes no erase resume
26 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c timing waveform for sector protection for system without 12v toe data oe# we# ce# a1 a6 * see the following note! verify 01h a18-a16 sector address 5v note1: must issue "unlock for sector protect/unprotect" command before sector protection for a system without 12v provided. note2: except f0h toggle bit polling don't care (note 2) tcep f0h
27 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c timing waveform for chip unprotection for system without 12v toe data we# ce# a1 verify 00h a6 note1: must issue "unlock for sector protect/unprotect" command before sector unprotection for a system without 12v provided. oe# tcep 5v toggle bit polling don't care (note 2) * see the following note! f0h note2: except f0h
28 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c sector protection algorithm for system without 12v start set up sector addr (a18, a17, a16) plscnt=1 sector protection complete data=01h? ye s oe#=vih,a9=vih ce#=vil,a6=vil activate we# pulse to start data don't care set ce#=oe#=vil a9=vih read from sector addr=sa, a1=1 protect another sector? write reset command device failed plscnt=32? ye s no increment plscnt no write "unlock for sector protect/unprotect" command(table1) toggle bit checking q6 not toggled no . ye s
29 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c chip unprotection algorithm for system without 12v start protect all sectors plscnt=1 chip unprotect complete data=00h? toggle bit checking q6 not toggled ye s ye s write "unlock for sector protect/unprotect" command (table 1) set oe#=a9=vih ce#=vil,a6=1 activate we# pulse to start data do'nt care set oe#=ce#=vil a9=vih,a1=1 set up first sector addr all sectors have been verified? write reset command device failed plscnt=1000? no increment plscnt no read data from device ye s ye s no no increment sector addr * it is recommended before unprotect whole chip, all sectors should be protected in advance.
30 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c id code read timing waveform tacc tce tacc toe toh toh tdf data out c2h a4h vid vih vil add a9 add a2-a8 a10-a18 ce# a1 oe# we# add a0 data out data q0-q7 vcc 5v vih vil vih vil vih vil vih vil vih vil vih vil vih vil
31 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c min. max. input voltage with respect to gnd on all pins except i/o pins -1.0v 13.5v input voltage with respect to gnd on all i/o pins -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 5.0v, one pin at a time. limits parameter min. typ.(2) max.(3) units sector erase time 0.7 15 sec chip erase time 4 32 sec byte programming time 9 300 us chip programming time 4.5 13.5 sec erase/program cycles 100,000 cycles latch-up characteristics erase and programming performance (1) note: 1.not 100% tested, excludes external system level over head. 2.typical values measured at 25 c,5v. 3.maximunm values measured at 25 c,4.5v. parameter min. unit data retention time 20 years data retention
32 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c ordering information part no. access time operating current standby current t emperature package remark (ns) max.(ma) max.(ua) range mx29f040cqi-55 55 30 5 -40 o c~85 o c 32 pin plcc mx29f040cqi-70 70 30 5 -40 o c~85 o c 32 pin plcc mx29f040cqi-90 90 30 5 -40 o c~85 o c 32 pin plcc mx29f040cti-55 55 30 5 -40 o c~85 o c 32 pin tsop (normal type) mx29f040cti-70 70 30 5 -40 o c~85 o c 32 pin tsop (normal type) mx29f040cti-90 90 30 5 -40 o c~85 o c 32 pin tsop (normal type) mx29f040cpi-55 55 30 5 -40 o c~85 o c 32 pin pdip mx29f040cpi-70 70 30 5 -40 o c~85 o c 32 pin pdip mx29f040cpi-90 90 30 5 -40 o c~85 o c 32 pin pdip mx29f040cqi-55g 55 30 5 -40 o c~85 o c 32 pin plcc pb free mx29f040cqi-70g 70 30 5 -40 o c~85 o c 32 pin plcc pb free mx29f040cqi-90g 90 30 5 -40 o c~85 o c 32 pin plcc pb free mx29f040cti-55g 55 30 5 -40 o c~85 o c 32 pin tsop pb free (normal type) mx29f040cti-70g 70 30 5 -40 o c~85 o c 32 pin tsop pb free (normal type) mx29f040cti-90g 90 30 5 -40 o c~85 o c 32 pin tsop pb free (normal type) mx29f040cpi-55g 55 30 5 -40 o c~85 o c 32 pin pdip pb free mx29f040cpi-70g 70 30 5 -40 o c~85 o c 32 pin pdip pb free mx29f040cpi-90g 90 30 5 -40 o c~85 o c 32 pin pdip pb free
33 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c part name description mx 29 f 70 c t i g option: g: lead-free package blank: normal speed: 55:55ns 70:70ns 90: 90ns temperature range: i: industrial (-40?ac to 85? c package: p: pdip q: plcc t: tsop revision: c density & mode: 040: 4, x8 equal sector type: f: 5v device: 29: flash 040
34 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c package information
35 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c
36 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c
37 p/n:pm1201 rev. 1.0, dec. 20, 2005 mx29f040c revision history revision no. description page date 1.0 1. removed "preliminary" title p1 dec/20/2005 2. removed commercial grade all 3. added access time: 55ns; removed access time: 120ns all
mx29f040c m acronix i nternational c o., l td . headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office : tel:+32-2-456-8020 fax:+32-2-456-8021 hong kong office : tel:+86-755-834-335-79 fax:+86-755-834-380-78 japan office : kawasaki office : tel:+81-44-246-9100 fax:+81-44-246-9105 osaka office : tel:+81-6-4807-5460 fax:+81-6-4807-5461 singapore office : tel:+65-6346-5505 fax:+65-6348-8096 taipei office : tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-262-8887 fax:+1-408-262-8810 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice.

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